diff --git a/fpga_device_manager/Banks.py b/fpga_device_manager/Banks.py
new file mode 100644
index 0000000000000000000000000000000000000000..2a63526beb894f4a7d5cb954709d7e7e6cf67f31
--- /dev/null
+++ b/fpga_device_manager/Banks.py
@@ -0,0 +1,43 @@
+"""Module that manages FPGA banks."""
+import json
+from typing import Optional, Tuple, Iterable, Generator, Iterator
+
+_banks = {}
+
+VOLTAGES = {1.2, 1.5, 1.8, 2.5, 3.3}
+
+
+class FPGABank:
+ """Represents a bank on the FPGA."""
+ def __init__(self, name, voltage=3.3):
+ self.name = name
+ self.voltage = voltage
+
+
+def init(filename: str) -> None:
+ """
+ Initializes the FPGA bank database by loading the bank configuration from the specified filename. The file must be
+ in JSON format and contains bank settings, indexed by the FPGA's bank names.
+
+ :param filename: FPGA bank configuration file
+ """
+ global _banks
+ _banks = {}
+
+ try:
+ with open(filename, "r") as file:
+ bank_data = json.load(file)
+
+ for bank, bank_args in bank_data.items():
+ voltage = bank_args["voltage"]
+ if voltage in VOLTAGES:
+ _banks[bank] = FPGABank(name=bank,
+ voltage=voltage)
+ else:
+ raise Exception("invalid voltage")
+
+ except OSError as e:
+ raise Exception("failed to load bank data file: %s" % e)
+
+def get_voltage(bank_id: int) -> float:
+ return _banks.get(str(bank_id), _banks["0"]).voltage
diff --git a/fpga_device_manager/Pins.py b/fpga_device_manager/Pins.py
index 92e91e0d23902bdd8b9a58eca828c56a5c81f1d4..d324fa6a8ea07d0b88aed0209001342d40342e5b 100755
--- a/fpga_device_manager/Pins.py
+++ b/fpga_device_manager/Pins.py
@@ -2,6 +2,8 @@
import json
from typing import Optional, Tuple, Iterable, Generator, Iterator
+from .Banks import get_voltage
+
_pins = {}
PIN_RESERVED = 0
@@ -22,7 +24,7 @@ _PIN_COLORS = {
class FPGAPin:
"""Represents a physical pin on the FPGA."""
def __init__(self, name, display_name=None, supports_pwm=True, supports_output=True, supports_input=True,
- fpga_addr=31, device_pin=None, voltage=True):
+ fpga_addr=31, device_pin=None, bank=None):
self.name = name
self.display_name = display_name or name
self.supports_pwm = supports_pwm
@@ -30,7 +32,7 @@ class FPGAPin:
self.supports_input = supports_input
self.fpga_addr = fpga_addr
self.device_pin = device_pin
- self.voltage = voltage
+ self.voltage = str(get_voltage(bank)).replace(".", "")
def is_assigned(self) -> bool:
"""
@@ -85,8 +87,8 @@ def init(filename: str) -> None:
in JSON format and contains pin settings, indexed by the FPGA's pin names. At the very least, each pin must
contain the properties 'addr' (an integer describing the pin's internal adress) and 'pwm' (a Boolean value
describing whether the pin supports PWM output). Optionally, it can also contain a 'name' attribute (a string
- overriding the FPGA pin name for the preview image) and 'output', 'input' and '3.3v' attributes (Boolean values
- describing whether the pin supports output, input or 3.3v, respectively, defaulting to True).
+ overriding the FPGA pin name for the preview image) and 'output' and 'input' attributes (Boolean values
+ describing whether the pin supports output or input, respectively, defaulting to True).
Example of a configuration file:
{
@@ -124,7 +126,7 @@ def init(filename: str) -> None:
supports_input=pin_args.get("input", True),
supports_output=pin_args.get("output", True),
fpga_addr=pin_args.get("addr", 31),
- voltage=pin_args.get("3.3v", True))
+ bank=pin_args["bank"])
except OSError as e:
raise Exception("failed to load pin data file: %s" % e)
diff --git a/fpga_device_manager/__main__.py b/fpga_device_manager/__main__.py
index d84be0285cb0d0bb2b0203b5d918658a1a8d39aa..1ee07ca9246c68a182adf581110f0df113e4e221 100755
--- a/fpga_device_manager/__main__.py
+++ b/fpga_device_manager/__main__.py
@@ -3,7 +3,7 @@ import sys
from qtpy import QtWidgets
-from fpga_device_manager import Devices, Inputs, Pins
+from fpga_device_manager import Devices, Inputs, Pins, Banks
from fpga_device_manager.windows.main_window import MainWindow
if __name__ == '__main__':
@@ -11,6 +11,7 @@ if __name__ == '__main__':
Devices.init(os.path.join(base_data_path, "device_types.json"))
Inputs.init(os.path.join(base_data_path, "input_types.json"))
+ Banks.init(os.path.join(base_data_path, "banks.json"))
Pins.init(os.path.join(base_data_path, "pins.json"))
# Create some directories if possible
diff --git a/fpga_device_manager/res/data/banks.json b/fpga_device_manager/res/data/banks.json
new file mode 100644
index 0000000000000000000000000000000000000000..e17e74122b5530e9001d86eb86223b3448098b3c
--- /dev/null
+++ b/fpga_device_manager/res/data/banks.json
@@ -0,0 +1,20 @@
+{
+ "0": {
+ "voltage": 3.3
+ },
+ "1": {
+ "voltage": 2.5
+ },
+ "2": {
+ "voltage": 3.3
+ },
+ "3": {
+ "voltage": 2.5
+ },
+ "4": {
+ "voltage": 3.3
+ },
+ "5": {
+ "voltage": 3.3
+ }
+}
\ No newline at end of file
diff --git a/fpga_device_manager/res/data/pins.json b/fpga_device_manager/res/data/pins.json
index 33cbbf23446da5158721ca4965d2b05976858d3b..9cae4063481dfa2d797985c392cba920fce834b2 100755
--- a/fpga_device_manager/res/data/pins.json
+++ b/fpga_device_manager/res/data/pins.json
@@ -1,415 +1,513 @@
{
"1": {
"pwm": true,
- "addr": 0
+ "addr": 0,
+ "bank": 5
},
"2": {
"pwm": true,
- "addr": 1
+ "addr": 1,
+ "bank": 5
},
"3": {
"pwm": true,
- "addr": 2
+ "addr": 2,
+ "bank": 5
},
"4": {
"pwm": true,
- "addr": 3
+ "addr": 3,
+ "bank": 5
},
"6": {
"pwm": true,
- "addr": 4
+ "addr": 4,
+ "bank": 5
},
"9": {
"pwm": true,
- "addr": 5
+ "addr": 5,
+ "bank": 5
},
"10": {
"pwm": true,
- "addr": 6
+ "addr": 6,
+ "bank": 5
},
"11": {
"pwm": true,
- "addr": 7
+ "addr": 7,
+ "bank": 5
},
"12": {
"pwm": true,
- "addr": 8
+ "addr": 8,
+ "bank": 5
},
"13": {
"pwm": true,
- "addr": 9
+ "addr": 9,
+ "bank": 4
},
"14": {
"pwm": true,
- "addr": 10
+ "addr": 10,
+ "bank": 4
},
"19": {
"pwm": true,
- "addr": 11
+ "addr": 11,
+ "bank": 4
},
"20": {
"pwm": true,
- "addr": 12
+ "addr": 12,
+ "bank": 4
},
"21": {
"pwm": true,
- "addr": 13
+ "addr": 13,
+ "bank": 4
},
"22": {
"pwm": true,
- "addr": 14
+ "addr": 14,
+ "bank": 4
},
"23": {
"pwm": true,
- "addr": 15
+ "addr": 15,
+ "bank": 4
},
"25": {
"pwm": true,
- "addr": 16
+ "addr": 16,
+ "bank": 3
},
"26": {
"pwm": true,
- "addr": 17
+ "addr": 17,
+ "bank": 3
},
"27": {
"pwm": true,
- "addr": 18
+ "addr": 18,
+ "bank": 3
},
"32": {
"pwm": true,
- "addr": 19
+ "addr": 19,
+ "bank": 3
},
"33": {
"pwm": true,
- "addr": 20
+ "addr": 20,
+ "bank": 3
},
"34": {
"pwm": true,
- "addr": 21
+ "addr": 21,
+ "bank": 3
},
"35": {
"pwm": true,
- "addr": 22
+ "addr": 22,
+ "bank": 3
},
"97": {
"pwm": true,
"input": false,
"name": "D1",
"addr": 23,
- "3.3v": false
+ "bank": 1
},
"98": {
"pwm": true,
"input": false,
"name": "D2",
"addr": 24,
- "3.3v": false
+ "bank": 1
},
"99": {
"pwm": true,
"input": false,
"name": "D3",
"addr": 25,
- "3.3v": false
+ "bank": 1
},
"100": {
"pwm": true,
"input": false,
"name": "D4",
"addr": 26,
- "3.3v": false
+ "bank": 1
},
"104": {
"pwm": true,
"input": false,
"name": "D5",
"addr": 27,
- "3.3v": false
+ "bank": 1
},
"105": {
"pwm": true,
"input": false,
"name": "D6",
"addr": 28,
- "3.3v": false
+ "bank": 1
},
"106": {
"pwm": true,
"input": false,
"name": "D7",
"addr": 29,
- "3.3v": false
+ "bank": 1
+ },
+ "107": {
+ "pwm": true,
+ "input": false,
+ "name": "D8",
+ "addr": 30,
+ "bank": 1
},
"38": {
"addr": 50,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"39": {
"addr": 51,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"40": {
"addr": 52,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"41": {
"addr": 53,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"42": {
"addr": 54,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"43": {
"addr": 55,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"44": {
"addr": 56,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"45": {
"addr": 57,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"47": {
"addr": 58,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"48": {
"addr": 59,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"49": {
"addr": 60,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"50": {
"addr": 61,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"52": {
"addr": 62,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"54": {
"addr": 63,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"55": {
"addr": 64,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"56": {
"addr": 65,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"57": {
"addr": 66,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"58": {
"addr": 67,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"59": {
"addr": 68,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"60": {
"addr": 69,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"61": {
"addr": 70,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"62": {
"addr": 71,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"65": {
"addr": 72,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"67": {
"addr": 73,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"68": {
"addr": 74,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"69": {
"addr": 75,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"70": {
"addr": 76,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"71": {
"addr": 77,
- "pwm": true
+ "pwm": true,
+ "bank": 2
},
"73": {
"addr": 100,
- "pwm": true
+ "pwm": true,
+ "bank": 1
},
"74": {
"addr": 101,
- "pwm": true
+ "pwm": true,
+ "bank": 1
},
"75": {
"addr": 102,
- "pwm": true
+ "pwm": true,
+ "bank": 1
},
"76": {
"addr": 103,
- "pwm": true
+ "pwm": true,
+ "bank": 1
},
"77": {
"addr": 104,
- "pwm": true
+ "pwm": true,
+ "bank": 1
},
"78": {
"addr": 105,
- "pwm": true
+ "pwm": true,
+ "bank": 1
},
"81": {
"addr": 106,
- "pwm": true
+ "pwm": true,
+ "bank": 1
},
"82": {
"addr": 107,
- "pwm": true
+ "pwm": true,
+ "bank": 1
},
"83": {
"addr": 108,
- "pwm": true
+ "pwm": true,
+ "bank": 1
},
"84": {
"addr": 109,
- "pwm": true
+ "pwm": true,
+ "bank": 1
},
"85": {
"addr": 110,
- "pwm": true
+ "pwm": true,
+ "bank": 1
},
"86": {
"addr": 111,
- "pwm": true
+ "pwm": true,
+ "bank": 1
},
"91": {
"addr": 112,
- "pwm": true
+ "pwm": true,
+ "bank": 1
},
"92": {
"addr": 113,
- "pwm": true
+ "pwm": true,
+ "bank": 1
},
"93": {
"addr": 114,
- "pwm": true
+ "pwm": true,
+ "bank": 1
},
"94": {
"addr": 115,
- "pwm": true
+ "pwm": true,
+ "bank": 1
},
"96": {
"addr": 116,
- "pwm": true
+ "pwm": true,
+ "bank": 1
},
"95": {
"addr": 117,
- "pwm": true
+ "pwm": true,
+ "bank": 1
},
"109": {
"addr": 150,
- "pwm": true
+ "pwm": true,
+ "bank": 0
},
"110": {
"addr": 151,
- "pwm": true
+ "pwm": true,
+ "bank": 0
},
"111": {
"addr": 152,
- "pwm": true
+ "pwm": true,
+ "bank": 0
},
"112": {
"addr": 153,
- "pwm": true
+ "pwm": true,
+ "bank": 0
},
"113": {
"addr": 154,
- "pwm": true
+ "pwm": true,
+ "bank": 0
},
"114": {
"addr": 155,
- "pwm": true
+ "pwm": true,
+ "bank": 0
},
"115": {
"addr": 156,
- "pwm": true
+ "pwm": true,
+ "bank": 0
},
"117": {
"addr": 157,
- "pwm": true
+ "pwm": true,
+ "bank": 0
},
"119": {
"addr": 158,
- "pwm": true
+ "pwm": true,
+ "bank": 0
},
"120": {
"addr": 159,
- "pwm": true
+ "pwm": true,
+ "bank": 0
},
"121": {
"addr": 160,
- "pwm": true
+ "pwm": true,
+ "bank": 0
},
"122": {
"addr": 161,
- "pwm": true
+ "pwm": true,
+ "bank": 0
},
"125": {
"addr": 162,
- "pwm": true
+ "pwm": true,
+ "bank": 0
},
"126": {
"addr": 163,
- "pwm": true
+ "pwm": true,
+ "bank": 0
},
"127": {
"addr": 164,
- "pwm": true
+ "pwm": true,
+ "bank": 0
},
"128": {
"addr": 165,
- "pwm": true
+ "pwm": true,
+ "bank": 0
},
"138": {
"addr": 166,
- "pwm": true
+ "pwm": true,
+ "bank": 0
},
"139": {
"addr": 167,
- "pwm": true
+ "pwm": true,
+ "bank": 0
},
"140": {
"addr": 168,
- "pwm": true
+ "pwm": true,
+ "bank": 0
},
"141": {
"addr": 169,
- "pwm": true
+ "pwm": true,
+ "bank": 0
},
"142": {
"addr": 170,
- "pwm": true
+ "pwm": true,
+ "bank": 0
},
"143": {
"addr": 171,
- "pwm": true
+ "pwm": true,
+ "bank": 0
}
}
diff --git a/fpga_device_manager/res/vtemplates/smarthome.lpf.tpl b/fpga_device_manager/res/vtemplates/smarthome.lpf.tpl
index c126d5475ec6c5050e5dff9ec105577a5ad1b5b8..72a1cf987b32d08096b9be7f79334df904f2f76f 100644
--- a/fpga_device_manager/res/vtemplates/smarthome.lpf.tpl
+++ b/fpga_device_manager/res/vtemplates/smarthome.lpf.tpl
@@ -9,7 +9,7 @@ LOCATE COMP "SDA" SITE "24" ;
// pin {{ pin.display_name }} on physical pin {{ pin.name }}
LOCATE COMP "pin_{{ pin.name }}" SITE "{{ pin.name }}" ;
-{% if pin.voltage %}IOBUF PORT "pin_{{ pin.name }}" IO_TYPE=LVCMOS33 ;{% endif %}
+IOBUF PORT "pin_{{ pin.name }}" IO_TYPE=LVCMOS{{ pin.voltage }} ;
{% endfor %}
LOCATE COMP "btn_reset" SITE "28" ;
\ No newline at end of file