diff --git a/README.md b/README.md
index 5a1dd608d023c3b51b83c0c41fc0cc821d088cd1..fac4a1db4eaf07e2c4dc7a31edef72ef03d18230 100644
--- a/README.md
+++ b/README.md
@@ -53,10 +53,15 @@ Verilog code can be generated from the command line like this:
 python -m fpga_device_manager.generator --output=./generated configuration.json
 ```
 
-### Valid configurations
+#### Valid configurations
 A valid configuration needs:
 
 - at least one appliance
 - at least one sensor
 - every sensor to be associated with an appliance
-- an I2C adress between 8 and 119 which is not dividable by 4 but by 2
+- an I2C adress
+
+#### Concept
+
+##### Banks
+The pins on the used MachXO2 FPGA board are classified into so-called banks - groups of nearby pins that share the same I/O voltage. By now, these voltages and the assignment of banks to pins can only be changed manually in the JSON configuration.