From 161049b9ea8835275ad4f202f4b7dc1255d99f43 Mon Sep 17 00:00:00 2001 From: Hangzhi Yu <hangzhi@protonmail.com> Date: Sat, 11 Sep 2021 17:37:02 +0000 Subject: [PATCH] Add readme section for banks --- README.md | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 5a1dd60..fac4a1d 100644 --- a/README.md +++ b/README.md @@ -53,10 +53,15 @@ Verilog code can be generated from the command line like this: python -m fpga_device_manager.generator --output=./generated configuration.json ``` -### Valid configurations +#### Valid configurations A valid configuration needs: - at least one appliance - at least one sensor - every sensor to be associated with an appliance -- an I2C adress between 8 and 119 which is not dividable by 4 but by 2 +- an I2C adress + +#### Concept + +##### Banks +The pins on the used MachXO2 FPGA board are classified into so-called banks - groups of nearby pins that share the same I/O voltage. By now, these voltages and the assignment of banks to pins can only be changed manually in the JSON configuration. -- GitLab