diff --git a/fpga_device_manager/windows/main_window.py b/fpga_device_manager/windows/main_window.py
index 2476658d4441498c4cb266265b7bc059b342e590..7189f0b154abace3dcfa0ec2aa0baccebbc3e658 100755
--- a/fpga_device_manager/windows/main_window.py
+++ b/fpga_device_manager/windows/main_window.py
@@ -153,6 +153,7 @@ class MainWindow(BaseWindow):
         :param path: Path to output Verilog files to
         """
         try:
+            self.refresh()
             Config.export(path)
             Popup.info(title="Successfully exported",
                        message=f"Verilog code has been successfully written to {path}.")