From c4b1ab6d4fedcc07a8df1da230aa69af01bbac2d Mon Sep 17 00:00:00 2001
From: Julian Leucker <leuckerj@gmail.com>
Date: Fri, 10 Jul 2020 17:18:10 +0200
Subject: [PATCH] Add voltage attribute to FPGAPin
---
fpga_device_manager/Pins.py | 19 ++++++++++---------
fpga_device_manager/res/data/pins.json | 24 ++++++++++++++++--------
2 files changed, 26 insertions(+), 17 deletions(-)
diff --git a/fpga_device_manager/Pins.py b/fpga_device_manager/Pins.py
index 4025979..92e91e0 100755
--- a/fpga_device_manager/Pins.py
+++ b/fpga_device_manager/Pins.py
@@ -22,7 +22,7 @@ _PIN_COLORS = {
class FPGAPin:
"""Represents a physical pin on the FPGA."""
def __init__(self, name, display_name=None, supports_pwm=True, supports_output=True, supports_input=True,
- fpga_addr=31, device_pin=None):
+ fpga_addr=31, device_pin=None, voltage=True):
self.name = name
self.display_name = display_name or name
self.supports_pwm = supports_pwm
@@ -30,6 +30,7 @@ class FPGAPin:
self.supports_input = supports_input
self.fpga_addr = fpga_addr
self.device_pin = device_pin
+ self.voltage = voltage
def is_assigned(self) -> bool:
"""
@@ -80,13 +81,12 @@ class FPGAPin:
def init(filename: str) -> None:
"""
- Initializes the FPGA pin database by loading the pin configuration from the specified filename.
- The file must be in JSON format and contains pin settings, indexed by the FPGA's pin names.
- At the very least, each pin must contain the properties 'addr' (an integer describing the pin's internal adress)
- and 'pwm' (a Boolean value describing whether the pin supports PWM output).
- Optionally, it can also contain a 'name' attribute (a string overriding the FPGA pin name for the preview image)
- and 'output' and 'input' attributes (Boolean values describing whether the pin supports output or input,
- respectively, defaulting to True).
+ Initializes the FPGA pin database by loading the pin configuration from the specified filename. The file must be
+ in JSON format and contains pin settings, indexed by the FPGA's pin names. At the very least, each pin must
+ contain the properties 'addr' (an integer describing the pin's internal adress) and 'pwm' (a Boolean value
+ describing whether the pin supports PWM output). Optionally, it can also contain a 'name' attribute (a string
+ overriding the FPGA pin name for the preview image) and 'output', 'input' and '3.3v' attributes (Boolean values
+ describing whether the pin supports output, input or 3.3v, respectively, defaulting to True).
Example of a configuration file:
{
@@ -123,7 +123,8 @@ def init(filename: str) -> None:
supports_pwm=pin_args["pwm"],
supports_input=pin_args.get("input", True),
supports_output=pin_args.get("output", True),
- fpga_addr=pin_args.get("addr", 31))
+ fpga_addr=pin_args.get("addr", 31),
+ voltage=pin_args.get("3.3v", True))
except OSError as e:
raise Exception("failed to load pin data file: %s" % e)
diff --git a/fpga_device_manager/res/data/pins.json b/fpga_device_manager/res/data/pins.json
index ada7436..81d83f7 100755
--- a/fpga_device_manager/res/data/pins.json
+++ b/fpga_device_manager/res/data/pins.json
@@ -95,49 +95,57 @@
"pwm": true,
"input": false,
"name": "D1",
- "addr": 23
+ "addr": 23,
+ "3.3v": false
},
"98": {
"pwm": true,
"input": false,
"name": "D2",
- "addr": 24
+ "addr": 24,
+ "3.3v": false
},
"99": {
"pwm": true,
"input": false,
"name": "D3",
- "addr": 25
+ "addr": 25,
+ "3.3v": false
},
"100": {
"pwm": true,
"input": false,
"name": "D4",
- "addr": 26
+ "addr": 26,
+ "3.3v": false
},
"104": {
"pwm": true,
"input": false,
"name": "D5",
- "addr": 27
+ "addr": 27,
+ "3.3v": false
},
"105": {
"pwm": true,
"input": false,
"name": "D6",
- "addr": 28
+ "addr": 28,
+ "3.3v": false
},
"106": {
"pwm": true,
"input": false,
"name": "D7",
- "addr": 29
+ "addr": 29,
+ "3.3v": false
},
"107": {
"pwm": true,
"input": false,
"name": "D8",
- "addr": 30
+ "addr": 30,
+ "3.3v": false
},
"38": {
"addr": 50,
--
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