Remove critical bug

fpga_device_manager/windows/main_window.py

@@ -153,6 +153,7 @@ class MainWindow(BaseWindow):
         :param path: Path to output Verilog files to
         """
         try:
+            self.refresh()
             Config.export(path)
             Popup.info(title="Successfully exported",
                        message=f"Verilog code has been successfully written to {path}.")